The Senior Digital Implementation Engineer is responsible for the end-to-end digital implementation of complex ASIC designs, including synthesis, place and route, and timing closure. This role requires strong technical skills and experience in digital design methodologies, along with a proven ability to work in a collaborative environment. The ideal candidate will lead implementation projects, mentor junior engineers, and drive continuous improvements in digital design flows and methodologies.

Key Responsibilities:

• Digital Design Implementation: Lead the synthesis, place and route, and optimization of complex digital designs, ensuring high performance, area efficiency, and low power consumption.
• Timing Closure: Perform static timing analysis and drive timing closure efforts for digital designs, identifying and resolving timing issues across multiple corners.
• Collaboration: Work closely with RTL designers, verification engineers, and physical design teams to ensure smooth integration and compliance with design specifications.
• Methodology Development: Develop and improve digital implementation methodologies and flows, including best practices for synthesis, place and route, and DFT.
• Tool Utilization: Utilize EDA tools (e.g., Synopsys Design Compiler, Cadence Innovus, or Mentor Graphics) effectively for implementation tasks and drive automation efforts for increased efficiency.
• Debugging and Troubleshooting: Identify and resolve implementation issues, including signal integrity, DRC/LVS errors, and timing violations, through thorough debugging and analysis.
• Documentation: Maintain comprehensive documentation of design processes, methodologies, and project deliverables, ensuring traceability and knowledge sharing.
• Mentorship: Provide technical guidance and mentorship to junior engineers, fostering their growth in digital design implementation and best practices.

• Bachelor’s in Electrical Engineering, Computer Engineering, or a related field. Master Degree is a plus
• 5-8 years of experience in digital design implementation, with a strong background in ASIC or FPGA design flows.
• Proven experience with multiple complete design cycles, from RTL to GDSII.
• Proficiency in RTL design languages (Verilog/SystemVerilog) and strong understanding of digital design concepts.
• In-depth knowledge of synthesis, place and route, and static timing analysis methodologies.
• Familiarity with design for test (DFT) methodologies and tools.
• Experience with EDA tools (e.g., Synopsys Design Compiler, Cadence Innovus, Mentor Graphics).
• Strong scripting skills (e.g., Perl, Tcl, Python) for automation and tool integration.